A Simple Circuit Approach to Improve Speed and Power Consumption in Pulse-Triggered Flip-Flops

In this paper, simple circuital techniques to design efficient pulse triggered flip-flops are presented. The proposed approach aims at considerably alleviating the detrimental effects of current contention mechanisms, occurring at critical switching nodes of the circuits. In this way, both latency and power consumption of pulse triggered flip-flops are reduced. The proposed approach is assessed by means of simulations in 90-nm ST commercial CMOS technology. When applied to some recently proposed implicit pulse triggered flip-flop architectures, the suggested design strategy, allows speed to be improved up to 13% and power-delay-product to be lowered down to 14%. Moreover, also the process variation tolerance is considerably improved.